1. Field of the Invention
The present invention relates to a wafer level package, and a manufacturing method thereof, and more particularly to a wafer level package and a manufacturing method thereof for forming a micro device, such as a film bulk acoustic resonator (hereinafter, referred to as an FBAR), into a chip scale package.
2. Description of the Related Art
According to recent rapid development of communication techniques, technical development of high frequency devices has become highly desirable. In response to such a demand, there was developed an FBAR device, which is a thin film filter device manufactured by depositing a piezoelectric material on a semiconductor substrate. Currently, the FBAR device is in the spotlight as an essential passive element in an RF wireless mobile communication field.
In general, micro devices such as FBAR devices are packaged to achieve a product such as a duplexer filter, and mounted to the product. Therefore, in order to achieve miniaturization in mobile communication products, it is necessary to reduce the overall size of an obtained micro device package.
Conventionally, the micro devices such as the FBAR devices are packaged by the use of a high temperature cofired ceramic (hereinafter, referred to as HTCC) substrate. FIG. 1 illustrates a conventional micro device package using such HTCC substrate.
As shown in FIG. 1, the conventional micro device package, designated as reference numeral 10, comprises a micro device 15, and an HTCC substrate 11 in which the micro device 15 is mounted. For the reception of the micro device 15, the HTCC substrate 11 is formed with a well 14. In a mounted state in the well 14, the micro device 15 is connected to bonding pads 12 placed on the HTCC substrate 11 through wires 19. Further, a cap layer 18 is formed over the HTCC substrate 11 in order to hermetically seal the well 14 in which the micro device 15 is mounted.
The micro device package 10 shown in FIG. 1 is manufactured by cutting a micro device prepared in wafer units while securing a sufficient chip die area, and then mounting the cut micro device in a structure having a size larger than that of the micro device. Such a micro device package 10 increases the size of a chip itself, and further the HTCC substrate 11 has a large size due to its stepped portion defined therein for the mounting of the micro device. Therefore, the conventional micro device package shown in FIG. 1 has a problem in that it is difficult to achieve miniaturization in the size of a final package. For example, in the case of an FBAR device package having a single FBAR device as shown in FIG. 1, since it has a size not less than 3 millimeters in length and width, it is very difficult to achieve a desired small size (for example, 5 millimeters in length and width) of a duplexer package having two FBAR devices.
In order to satisfy such a miniaturization demand, currently, there has been developed a wafer-level chip-scale package technique utilizing a certain process carried out at the wafer level where a micro device is formed. Such a wafer-level chip-scale package utilizes a cap structure, such as a cap wafer processed for the formation of a terminal. FIG. 2 is a side sectional view illustrating a conventional wafer level package using a cap wafer.
Referring to FIG. 2, the wafer level package, designated as reference numeral 40, comprises a device wafer 20 formed with a micro device 25 such as an FBAR device, and a cap wafer 30. The device wafer 20 includes electrical bonding pads 21 for use in the driving of the micro device 25 formed at the upper surface of the device wafer 20, and a peripheral pad 22 placed around the perimeter of the device wafer 20. The cap wafer 30 is formed with via holes H at some portions corresponding to the bonding pads 21 so as to allow the bonding pads 21 to be connected to certain external circuits (not shown) by bonding wires 39 therebetween.
In order to secure operational reliability of the micro device 25, between the cap wafer 30 and the device wafer 20 are provided first and second sealing members 23 and 24. Each of the first sealing members 23 is formed to have a ring shape, so that it is placed along the periphery of the respective bonding pads 21 for use in wire bonding, in order to prevent the micro device 25 from being exposed to the outside through the via holes H. The second sealing member 24 is formed on the peripheral pad 22 along the perimeter of the wafer level package 40.
Although the wafer level package 40 using a micro cap as shown in FIG. 2 is advantageous in miniaturization compared with a conventional wafer level package using an HTCC substrate, since the via holes H should be previously formed so as to correspond to the bonding pads 21, respectively, the processing of the cap wafer 30 is complex, resulting in difficulty in the overall manufacturing process thereof.
Further, as stated above, the wafer level package 40 shown in FIG. 2 should have the first sealing members 23, in order to prevent the micro device 25 from being exposed to the outside through the via holes H formed at the cap wafer 30 for connecting the bonding pads 21 provided on the device wafer 20 to certain external circuits. In this case, it is essential for the first sealing members 23 to be made of metal sealing members since they are formed on the metal bonding pads 21.
For the above reasons, there has been a need for a rigid chip scale wafer level package and a manufacturing method thereof, which can improve an overall yield by simplifying a process related with a cap structure such as a cap wafer, and secure the complete air-tight of the wafer level package.